Mobile Memory Cache Read Optimization

ABSTRACT

Examples of enabling cache read optimization for mobile memory devices are described. One or more access commands may be received, from a host, at a memory device. The one or more access commands may instruct the memory device to access at least two data blocks. The memory device may generate pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks.

RELATED APPLICATION

This application is a continuation of and claims priority to U.S. patentapplication Ser. No. 14/020,527, filed on Sep. 6, 2013, which is acontinuation of U.S. patent application Ser. No. 13/179,689, filed onJul. 11, 2011, now U.S. Pat. No. 8,560,778, Issued on Oct. 15, 2013. Theentire contents of U.S. patent application Ser. Nos. 14/020,527 and13/179,689 and U.S. Pat. No. 8,560,778 are fully incorporated byreference herein.

TECHNICAL FIELD

The exemplary and non-limiting embodiments of this invention relategenerally to memory devices and, more specifically, relate to providingcache read optimization for mobile memory devices.

BACKGROUND

This section is intended to provide a background or context to theinvention that is recited in the claims. The description herein mayinclude concepts that could be pursued, but are not necessarily onesthat have been previously conceived or pursued. Therefore, unlessotherwise indicated herein, what is described in this section is notprior art to the description and claims in this application and is notadmitted to be prior art by inclusion in this section.

The following abbreviations that may be found in the specificationand/or the drawing figures are defined as follows:

DB database

DRAM dynamic random access memory

ECC error correction code

e-MMC embedded MultiMediaCard

eNB E-UTRAN Node B (evolved Node B)

FW firmware

HW hardware

Node B base station

OS operating system

PC personal computer

SBC(-3) SCSI block commands

SCSI small computer system interface

SSD solid state disc

SW software

UE user equipment, such as a mobile station or mobile terminal

UFS universal flash storage

Mobile devices, such as UEs, may use memory for storing user data, forexample, music, pictures, applications, maps, etc. The amount of userdata stored in mobile devices is increasing and will continue to grow.Some high-end devices provide user data storage based on non-volatilememory such as NAND memory technology (also known as flash memory). NANDmemory usage has expanded to mid-range devices.

In typical mobile managed NAND devices no actual cache memory exists dueto cost and power optimizations. There may be some memory controllerSRAM and a buffer memory in the NAND itself. However, these aretemporary storages to buffer the data before it is programmed into NANDmemory or delivered to the host. In some PC markets, managed NANDdevices, like SSDs, may have cache memory storage, typically DRAM,included in the memory device. In SSD, the data may be stored to a DRAMcache for longer periods of time before flushing it to the NAND storage.

The standardized cache definitions and improvement of performance applymainly for write operations. The existing standardized pre-fetch/packedcommand mechanisms are based on the host knowing which data should befetched next in order to provide the address to the device in advance.However, this is not always the case.

What is needed is a way to improve memory reads in NAND memory devices.

SUMMARY

The below summary section is intended to be merely exemplary andnon-limiting.

The foregoing and other problems are overcome, and other advantages arerealized, by the use of the exemplary embodiments of this invention.

In a first aspect thereof an exemplary embodiment of this inventionprovides a method for enabling cache read optimization for mobile memorydevices. The method includes receiving (e.g., at a processor) one ormore access commands, at a memory device from a host, the one or moreaccess commands instructing the memory device to access at least twodata blocks. Accessing the at least two data blocks is also included.The method includes generating, by the memory device, pre-fetchinformation for the at least two data blocks based at least in part onan order of accessing the at least two data blocks.

In a further aspect thereof an exemplary embodiment of this inventionprovides an apparatus for enabling cache read optimization for mobilememory devices. The apparatus includes one or more processors; and oneor more memories including computer program code, the one or morememories and the computer program code configured to, with the one ormore processors, cause the apparatus to perform actions. The actionsinclude to receive one or more access commands, at a memory device froma host, the one or more access commands instructing the memory device toaccess at least two data blocks. The at least two data blocks areaccessed. The actions also include to generate, by the memory device,pre-fetch information for the at least two data blocks based at least inpart on an order of accessing the at least two data blocks.

In another aspect thereof an exemplary embodiment of this inventionprovides a computer readable medium for enabling cache read optimizationfor mobile memory devices. The computer readable medium is tangiblyencoded with a computer program executable by a processor to performactions. The actions include receiving one or more access commands, at amemory device from a host, the one or more access commands instructingthe memory device to access at least two data blocks. The at least twodata blocks are accessed. The actions also include generating, by thememory device, pre-fetch information for the at least two data blocksbased at least in part on an order of accessing the at least two datablocks.

In a further aspect thereof an exemplary embodiment of this inventionprovides an apparatus for enabling cache read optimization for mobilememory devices. The apparatus includes means for receiving one or moreaccess commands, at a memory device from a host, the one or more accesscommands instructing the memory device to access at least two datablocks; means for accessing the at least two data blocks; and means forgenerating, by the memory device, pre-fetch information for the at leasttwo data blocks based at least in part on an order of accessing the atleast two data blocks.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other aspects of exemplary embodiments of thisinvention are made more evident in the following Detailed Description,when read in conjunction with the attached Drawing Figures, wherein:

FIG. 1 shows a simplified block diagram of exemplary electronic devicesthat are suitable for use in practicing various exemplary embodiments ofthis invention.

FIG. 2 shows a more particularized block diagram of an exemplary userequipment such as that shown at FIG. 1.

FIG. 3 shows a more particularized block diagram of an exemplary memorydevice such as that shown at FIGS. 1 and 2.

FIG. 4 shows a more particularized block diagram of an exemplary memoryunit as that shown at FIG. 3.

FIG. 5 illustrates exemplary memory write operations in accordance withthis invention.

FIG. 6 is a logic flow diagram that illustrates the operation of anexemplary method, and a result of execution of computer programinstructions embodied on a computer readable memory, in accordance withvarious exemplary embodiments of this invention.

DETAILED DESCRIPTION

As NAND read access time may be on the scale of tens of microseconds, itwould be advantageous that the next data could be fetched at least tothe buffers of the NAND device or to a controller's buffers/cache witherror correction code (ECC) corrected, in advance to a request for thedata so that when host requests the next data it could be delivered fromthe cache. This could increase the average speed of read operationswithout burdening the host processors. Additionally, as the accessrequests are served more quickly, the memory module can be put to lowpower state sooner providing a measure of power consumptionoptimization. Additionally, the linking of data may be improved in orderto ensure the correct data is fetched.

Before describing in further detail various exemplary embodiments ofthis invention, reference is made to FIG. 1 for illustrating asimplified block diagram of various electronic devices and apparatusthat are suitable for use in practicing exemplary embodiments of thisinvention.

In the wireless system 230 of FIG. 1, a wireless network 235 is adaptedfor communication over a wireless link 232 with an apparatus, such as amobile communication device which may be referred to as a UE 210, via anetwork access node, such as a Node B (base station), and morespecifically an eNB 220.

The UE 210 includes a controller, such as a computer or a data processor(DP) 214, a computer-readable memory medium embodied as a memory (MEM)216 that stores a program of computer instructions (PROG) 218, and asuitable wireless interface, such as radio frequency (RF) transceiver212, for bidirectional wireless communications with the eNB 220 via oneor more antennas. The UE 210 may also include one or more dedicatedprocessors, for example memory processor 215.

The PROGs 218 is assumed to include program instructions that, whenexecuted by the associated DP 214, enable the device to operate inaccordance with exemplary embodiments of this invention, as will bediscussed below in greater detail.

That is, various exemplary embodiments of this invention may beimplemented at least in part by computer software executable by the DP214 of the UE 210, or by hardware, or by a combination of software andhardware (and firmware).

In general, the various embodiments of the UE 210 can include, but arenot limited to, cellular telephones, personal digital assistants (PDAs)having wireless communication capabilities, portable computers havingwireless communication capabilities, image capture devices such asdigital cameras, gaming devices, music storage and playback appliances,Internet appliances permitting wireless Internet access and browsing, aswell as portable units or terminals that incorporate combinations ofsuch functions.

The computer readable MEM 216 may be of any type suitable to the localtechnical environment and may be implemented using any suitable datastorage technology, such as semiconductor based memory devices, flashmemory, magnetic memory devices and systems, optical memory devices andsystems, fixed memory and removable memory. The DP 214 may be of anytype suitable to the local technical environment, and may include one ormore of general purpose computers, special purpose computers,microprocessors, digital signal processors (DSPs) and processors basedon a multicore processor architecture, as non-limiting examples. Thewireless interface (e.g., RF transceiver 212) may be of any typesuitable to the local technical environment and may be implemented usingany suitable communication technology such as individual transmitters,receivers, transceivers or a combination of such components.

FIG. 2 illustrates further detail of an exemplary UE in both plan view(left) and sectional view (right), and the invention may be embodied inone or some combination of those more function-specific components. AtFIG. 2 the UE 210 has a graphical display interface 320 and a userinterface 322 illustrated as a keypad but understood as alsoencompassing touch-screen technology at the graphical display interface320 and voice-recognition technology received at the microphone 324. Apower actuator 326 controls the device being turned on and off by theuser. The exemplary UE 210 may have a camera 328 which is shown as beingforward facing (e.g., for video calls) but may alternatively oradditionally be rearward facing (e.g., for capturing images and videofor local storage). The camera 328 is controlled by a shutter actuator330 and optionally by a zoom actuator 332 which may alternativelyfunction as a volume adjustment for the speaker(s) 334 when the camera328 is not in an active mode.

Within the sectional view of FIG. 2 are seen multiple transmit/receiveantennas 336 that are typically used for cellular communication. Theantennas 336 may be multi-band for use with other radios in the UE. Theoperable ground plane for the antennas 336 is shown by shading asspanning the entire space enclosed by the UE housing though in someembodiments the ground plane may be limited to a smaller area, such asdisposed on a printed wiring board on which the power chip 338 isformed. The power chip 338 controls power amplification on the channelsbeing transmitted and/or across the antennas that transmitsimultaneously where spatial diversity is used, and amplifies thereceived signals. The power chip 338 outputs the amplified receivedsignal to the radio-frequency (RF) chip 340 which demodulates anddownconverts the signal for baseband processing. The baseband (BB) chip342 detects the signal which is then converted to a bit-stream andfinally decoded. Similar processing occurs in reverse for signalsgenerated in the apparatus 210 and transmitted from it.

Signals to and from the camera 328 pass through an image/video processor344 which encodes and decodes the various image frames. A separate audioprocessor 346 may also be present controlling signals to and from thespeakers 334 and the microphone 324. The graphical display interface 320is refreshed from a frame memory 348 as controlled by a user interfacechip 350 which may process signals to and from the display interface 320and/or additionally process user inputs from the keypad 322 andelsewhere.

Certain embodiments of the UE 210 may also include one or more secondaryradios such as a wireless local area network radio WLAN 337 and aBluetooth® radio 339, which may incorporate an antenna on-chip or becoupled to an off-chip antenna. Throughout the apparatus are variousmemories such as random access memory RAM 343, read only memory ROM 345,and in some embodiments removable memory such as the illustrated memorycard 347. The various programs 218 may be stored in one or more of flash333, e.g., NAND, eMMC, UFS, SSD, etc. All of these components within theUE 210 are normally powered by a portable power supply such as a battery349.

Processors 338, 340, 342, 344, 346, 350, if embodied as separateentities in a UE 210, may operate in a slave relationship to the mainprocessor 214, which may then be in a master relationship to them.Embodiments of this invention are most relevant to the controllers ofthe memory modules (333, 343, 345, 347, 348), though it is noted thatother embodiments need not be disposed there but may be disposed acrossvarious chips and memories as shown or disposed within another processorthat combines some of the functions described above for FIG. 2. Any orall of these various processors of FIG. 2 access one or more of thevarious memories, which may be on-chip with the processor or separatetherefrom.

Note that the various chips (e.g., 338, 340, 342, etc.) that weredescribed above may be combined into a fewer number than described and,in a most compact case, may all be embodied physically within a singlechip.

FIG. 3 shows a more particularized block diagram of an exemplary memorydevice such as that shown at FIGS. 1 and 2, e.g., MEM 216, RAM 343, ROM345, flash 333 and memory card 347. MEM 410 includes a memory controller(MC) 420 and, as shown, two individual memory units MEM 430 and MEM 440.In another exemplary embodiment, there may be one or more memory units.MC 420 is configured to handle read/write requests and send instructionsto MEM 430 and MEM 440 accordingly.

MEM 430 and MEM 440 may be the same type of memory device (e.g., bothusing NAND memory technology) or they may be of different types (e.g.,MEM 430 may use NAND memory technology and 440 may be an optical drivememory technology). Additionally, one or more of the memory units (MEM430, 440) may be used as a local cache memory for the MC 420.

FIG. 4 shows a more particularized block diagram of an exemplary memoryunit as that shown at FIG. 3. MEM 430 is divided into various memoryregions (432, 434, 436 and 438). Four regions are shown as anon-limiting illustration; however, there can be any number of regions(e.g., 1, 2, 4, 8, etc.).

The separation of the regions may be physical or a virtual/logicalseparation. A virtual separation may be performed by assigning variousmemory addresses to a region. The cells in a region may or may not bephysically contiguous. Each region may be treated separately by the MC420 or combined into a single entity.

As a non-limiting example, the MEM 430 may be separated into a largenumber of regions each representing a page of memory or a block ofmemory (e.g., a block of 512 bytes).

In a first exemplary embodiment in accordance with this invention, thepre-fetch/caching is tied to an index identifier (e.g., the ContextIDfeature of eMMC). Whenever the host writes to an index identifier (e.g.,index #1), the data written in the corresponding NAND block may includea link to the next index #1 data. This way, the host could operate asthough writing data (e.g., software (SW), picture/music data or databaseinformation) into a single index and, when reading the data (e.g., evenusing several sequential or single block read accesses), the next datamay be pre-fetched without additional host effort. In one non-limitingexample, the data TAG concept of eMMC or Group Number scheme of SCSISBC-3 may be used tying the data together for optimized read caching.

If the host later writes new data into the memory, it could use the sameindex used earlier (e.g. in production for writing the OS). In order tosupport a limited number of dynamic indices, every time a new index isopened only the latest data for that index will be linked together.Thus, any intervening write command could prevent a pre-fetch linkbetween write commands with the same index as these indices may or maynot correspond to the same data.

Alternatively, the index could be also fixed so that if new data islater written to an index which was closed earlier (e.g., the index isre-opened) then this new data would be linked to the end of the previouswrite. Indices may be fixed for an unlimited time, or may be fixedtemporarily (e.g., for a period of time, until the system is idle for apredetermined amount of time, in response to command, etc.).

A linking session may represent when data from write commands having thesame index information are linked. A new session is started when apreviously used index is used but blocks from the previous use are notto be linked to the new blocks (e.g., the last block of the previous useis not linked to the first block of the new use).

Additionally, a linking session may be ended due to any one of a numberof situations:

1) after a period of time from the initial starting of the linkingsession (e.g., a limited window),

2) after a period of time from the last access operation (e.g., atimeout after an idle period),

3) based on a state of the memory device (e.g. in eMMC: transfer stateor standby state, in UFS: linked to power modes or active LUs, etc.) or

4) a control register which changes the behavior in a host controlledtechnique.

In a memory device driven embodiment, the host does not need to utilizeany tags or indices, rather, the memory device controls the pre-fetch.In a first example, the memory device enforces pre-fetch of a nextlogical data or physical address data to buffers/cache. This would beefficient with data that was written into sequential (logical) addresseswith a ‘write multiple block’ command (e.g., the Write_Multiple_Blockscommand of eMMC). The device could also link such data together for readpre-fetch.

Alternatively, the last address of a previous write multiple blockcommand could be tied to a first address of the next write multipleblock command under the assumption that they belong to the samesequential file (e.g., megabytes of a data/file are typically cut intosmaller pieces for writing).

In a further exemplary embodiment in accordance with this invention, thememory device may link similar “random” accesses together. For example,where the file system of the media is very fragmented and data iswritten in very small pieces (small allocation unit granularity)throughout the memory media.

The memory device may determine linkages during the usage of data (forexample, where the host interaction is limited). Where the memory devicelinks two consecutive write accesses (e.g., to blocks A and B), theblocks may actually belong to different files/entities, thus, creating a“cache miss” when subsequently pre-fetched. These incorrect linkagescould be detected during use, for example, where the memory devicedetects that after a last address of A there is no subsequent reading ofthe first address of B indicating that the link between A and B may beremoved.

Additionally, if the memory device determines that after the lastaddress of A is accessed the first address of C is read then this linkcould be built during runtime.

In a further exemplary embodiment, more than one potential next addressmay be pre-fetched to the cache. For example, if there is no clear ideawhich data would be most advantageous to be pre-fetched if thesubsequent accesses change regularly according to some rule which maynot be known by the memory device.

Linkage information between a first block and a second block may bestored in a variety of ways. For example, the linkage information may besaved in the first block as a pointer to the second block. The secondblock may also store a pointer to the first block. Alternatively, thelinkage information may be saved in a separate location, for example, aspart of a list of linkages throughout the memory.

A block may also record linkage information indicating a plurality ofblocks, for example, where a second block was written immediately afterthe first block and a third block is read following the first block orwhere subsequent read operations alternate between a limited set ofblocks.

The linkage information may also include additional data. A count ofeach time a given block is read and no block is subsequently read withina given time may be used in order to determine when to break (or remove)a link to a subsequent block. A count for each block linked may also bekept representing the number of time that the specific block issubsequently read. This count may be used to determine which block(s) topre-fetch, for example, when pre-fetching only one block, the block withthe most subsequent reads may be used.

In some embodiments, the host may enable/disable linking addresses inthe writing phase or in the reading phase (e.g., through explicitsignaling) in order to optimize between access time vs. power. Thepre-fetch operations may be enabled/disabled (e.g., by the host) orestablished by a fixed setting for either the whole media or perpartition or logical unit.

The host may also instruct the memory device to cease pre-fetchoperations, for example, by changing a bit flag in a message. In anon-limiting example, the bit flag is a abort pre-fetch (ABPF) bit.

Additionally, the host may instruct the memory device whether or not tolink (or pre-fetch) data across physical memory devices. Thus, thememory device, in one setting, may link data blocks written to separatephysical devices (e.g., two distinct NAND memories), and in a secondsetting, no linking information would be generated.

FIG. 5 illustrates exemplary memory write operations in accordance withthis invention.

In a first example (1), the host issues a first write multiple blockscommand (e.g., a combined CMD23 and CMD25) and the memory returns aresponse (RESP). In this scenario, no context ID, TAG or specific ruleis provided by the host. The first write command instructs the memory towrite two 512 byte blocks (or pages) into memory. The blocks may includea cyclic redundancy check (CRC) or a corresponding CRC may be written toanother location. The write procedure creates a first indicator, A (apre-fetch link), linking the most recently written block (the firstblock) to the second block. Similarly, when the host issues a secondwrite command creating a third block, the memory device creates a secondindicator, B, linking the most recently written block (the second block)to the third block.

In a second example (2), the host provides context IDs or TAGs. In thefirst portion, the first write command instructs the memory to write two512 byte blocks (or pages) into memory using a first identifier (e.g.,#ID=1, TAG=X, etc.). When the host issues a second write command usingthe same identifier, the memory device creates an indicator, C, linkingthe most recently written block with the same identifier (the secondblock) to the third block. In the second portion (to the right of thehashed line), each write command is a separate program session whetheror not they share identifiers. As shown, when writing to an identifier(e.g., #ID=2, TAG=Y, etc.), an indicator, D, is omitted creating a breakin the pre-fetch link due to the program session being closed.

In a third example (3), the host again provides context IDs or TAGs. Asin example 2, an indicator, C, is created linking the most recentlywritten block with the same identifier (the second block) to the thirdblock. The procedure may create links between blocks even when otherwrite commands with different identifiers (e.g., the third writecommand) are performed. Thus, when the host issues a fourth writecommand using the same identifier as the first two write commands, thememory device creates an indicator, E, linking the most recently writtenblock with the same identifier (the fourth block) to the seventh block.

While not shown in examples 2 and 3, two blocks written in response to asingle write command may (or may not) have indicators linking them.These indicators may differ from those linking blocks written bydifferent write commands.

Based on the foregoing it should be apparent that the exemplaryembodiments of this invention provide a method, apparatus and computerprogram(s) to provide cache read optimization for mobile memory devices.

FIG. 6 is a logic flow diagram that illustrates the operation of amethod, and a result of execution of computer program instructions, inaccordance with the exemplary embodiments of this invention. Inaccordance with these exemplary embodiments a method performs, at Block610, a step of receiving at least one write command, at a memory deviceform a host. The at least one write command instructs the memory deviceto store at least two data blocks. The at least two data blocks arestored at Block 620. At Block 630, the memory device generates pre-fetchinformation for the at least two data blocks based at least in part onan order of storing the at least two data blocks.

The various blocks shown in FIG. 6 may be viewed as method steps, and/oras operations that result from operation of computer program code,and/or as a plurality of coupled logic circuit elements constructed tocarry out the associated function(s).

In general, the various exemplary embodiments may be implemented inhardware or special purpose circuits, software, logic or any combinationthereof. For example, some aspects may be implemented in hardware, whileother aspects may be implemented in firmware or software which may beexecuted by a controller, microprocessor or other computing device,although the invention is not limited thereto. While various aspects ofthe exemplary embodiments of this invention may be illustrated anddescribed as block diagrams, flow charts, or using some other pictorialrepresentation, it is well understood that these blocks, apparatus,systems, techniques or methods described herein may be implemented in,as non-limiting examples, hardware, software, firmware, special purposecircuits or logic, general purpose hardware or controller or othercomputing devices, or some combination thereof.

In an exemplary embodiment in accordance with this invention, a methodis provided for enabling cache read optimization for mobile memorydevices. The method includes receiving (e.g., at a processor) one ormore access commands, at a memory device from a host, the one or moreaccess commands instructing the memory device to access at least twodata blocks. Accessing (e.g., by a processor) the at least two datablocks is also included. The method includes generating (e.g., by aprocessor), by the memory device, pre-fetch information for the at leasttwo data blocks based at least in part on an order of accessing the atleast two data blocks.

In a further exemplary embodiment of the method above, generating thepre-fetch information is further based on information provided by thehost, and/or rules in a controller for the memory device.

In another exemplary embodiment of any one of the methods above, eachaccess command of the one or more access commands is associated withindex information including a context identifier, a task tag, apre-fetch identifier and/or a group number. The index information may besent with the access command or in a separate message.

In a further exemplary embodiment of the method above, the one or moreaccess commands include a first access command and a second accesscommand. The first access command and the second access command includeidentical index information.

In another exemplary embodiment of the method above, receiving the oneor more access commands include receiving a first access command at afirst time including first index information, receiving a second accesscommand at a second time after the first time, where the second accesscommand includes second index information which differs from the firstindex information, and receiving a third access command at a third timeafter the second time including the first index information.

In a further exemplary embodiment of the method above, generating thepre-fetch information includes linking a last data block accessed inresponse to the first access command to a first data block accessed inresponse to the third access command.

In another exemplary embodiment of the method above, generating thepre-fetch information includes starting a new linking data session for afirst data block accessed in response to the third access command. Datablocks accessed in response to access commands having the same indexinformation are linked during a linking data session.

In a further exemplary embodiment of the method above, data blocksaccessed in response to access commands having matching indexinformation are linked during a linking data session, and the methodalso includes starting a new linking data session in response to anelapse of a predetermined time after a previous access commands havingthe matching index information, an elapse of time after the linking datasession was started, or a change in a control register.

In another exemplary embodiment of any one of the methods above,generating the pre-fetch information includes linking a first data blockof the at least two data blocks to a next subsequently accessed datablock of the at least two data blocks.

In a further exemplary embodiment of any one of the methods above, theone or more access commands include a read command and/or a writecommand.

In another exemplary embodiment of any one of the methods above, thepre-fetch information includes instructions to pre-fetch at least twoblocks when a first block is read.

In a further exemplary embodiment of any one of the methods above, themethod also includes receiving a first read command instructing thememory device to provide a first read data block to the host; providingthe first read data block to the host; determining a subsequent readdata block based on the pre-fetch information; pre-fetching thesubsequent read data block; after pre-fetching the subsequent read datablock, receiving a second read command instructing the memory device toprovide the subsequent read data block to the host; and providing thepre-fetched subsequent read data block to the host.

In another exemplary embodiment of the method above, the method alsoincludes receiving a command to cease generating pre-fetch informationfor at least a portion of the memory device; and preventing generatingpre-fetch information when accessing data blocks in the portion of thememory device.

In a further exemplary embodiment the method above, the method alsoincludes receiving one or more additional access commands instructingthe memory device to access one or more of the two or more data blocks;and removing the pre-fetch information based on an order of data blocksaccessed in response to the one or more access commands.

In another exemplary embodiment of any one of the methods above, thememory device includes one or more NAND memory storage devices.

In another exemplary embodiment in accordance with this invention, anapparatus is provided for enabling cache read optimization for mobilememory devices. The apparatus includes one or more processors; and oneor more memories including computer program code, the one or morememories and the computer program code configured to, with the one ormore processors, cause the apparatus to perform actions. The actionsinclude to receive one or more access commands, at a memory device froma host, the one or more access commands instructing the memory device toaccess at least two data blocks. The at least two data blocks areaccessed. The actions also include to generate, by the memory device,pre-fetch information for the at least two data blocks based at least inpart on an order of accessing the at least two data blocks.

In another exemplary embodiment of the apparatus above, generating thepre-fetch information is further based on information provided by thehost, and/or rules in a controller for the memory device.

In a further exemplary embodiment of any one of the apparatus above,each access command of the one or more access commands is associatedwith index information including a context identifier, a task tag, apre-fetch identifier and/or a group number.

In another exemplary embodiment of the apparatus above, the one or moreaccess commands include a first access command and a second accesscommand, and the first access command and the second access commandinclude identical index information.

In a further exemplary embodiment of the apparatus above, when receivingthe one or more access commands, the one or more memories and thecomputer program code are further configured to cause the apparatus toreceive a first access command at a first time including first indexinformation, to receive a second access command at a second time afterthe first time, where the second access command includes second indexinformation which differs from the first index information, and toreceive a third access command at a third time after the second timeincluding the first index information.

In another exemplary embodiment of the apparatus above, when generatingthe pre-fetch information, the one or more memories and the computerprogram code are further configured to cause the apparatus to link lastdata block accessed in response to the first access command to a firstdata block accessed in response to the third access command.

In a further exemplary embodiment of the apparatus above, whengenerating the pre-fetch information, the one or more memories and thecomputer program code are further configured to cause the apparatus tostart a new linking data session for a first data block accessed inresponse to the third access command. Data blocks accessed in responseto access commands having the same index information are linked during alinking data session.

In another exemplary embodiment of the apparatus above, data blocksaccessed in response to access commands having matching indexinformation are linked during a linking data session, and the one ormore memories and the computer program code are further configured tocause the apparatus to start a new linking data session in response toan elapse of a predetermined time after a previous access commandshaving the matching index information, an elapse of time after thelinking data session was started, or a change in a control register.

In a further exemplary embodiment of any one of the apparatus above,when generating the pre-fetch information, the one or more memories andthe computer program code are further configured to cause the apparatusto link a first data block of the at least two data blocks to a nextsubsequently accessed data block of the at least two data blocks.

In another exemplary embodiment of any one of the apparatus above, theone or more access commands include a read command and/or a writecommand.

In a further exemplary embodiment of any one of the apparatus above, thepre-fetch information include instructions to pre-fetch at least twoblocks when a first block is read.

In another exemplary embodiment of any one of the apparatus above, theone or more memories and the computer program code are furtherconfigured to cause the apparatus to receive a first read commandinstructing the memory device to provide a first read data block to thehost; to provide the first read data block to the host; to determine asubsequent read data block based on the pre-fetch information; topre-fetch the subsequent read data block; after pre-fetching thesubsequent read data block, to receive a second read command instructingthe memory device to provide the subsequent read data block to the host;and to provide the pre-fetched subsequent read data block to the host.

In a further exemplary embodiment of the apparatus above, the one ormore memories and the computer program code are further configured tocause the apparatus to receive a command to cease generating pre-fetchinformation for at least a portion of the memory device; and to preventgenerating pre-fetch information when accessing data blocks in theportion of the memory device.

In another exemplary embodiment of any one of the apparatus above, theone or more memories and the computer program code are furtherconfigured to cause the apparatus to receive one or more additionalaccess commands instructing the memory device to access one or more ofthe two or more data blocks; and to remove the pre-fetch informationbased on an order of data blocks accessed in response to the one or moreaccess commands.

In a further exemplary embodiment of any one of the apparatus above, theapparatus is embodied in an integrated circuit.

In another exemplary embodiment in accordance with this invention, acomputer readable medium is provided for enabling cache readoptimization for mobile memory devices. The computer readable medium istangibly encoded with a computer program executable by a processor toperform actions. The actions include receiving one or more accesscommands, at a memory device from a host, the one or more accesscommands instructing the memory device to access at least two datablocks. The at least two data blocks are accessed. The actions alsoinclude generating, by the memory device, pre-fetch information for theat least two data blocks based at least in part on an order of accessingthe at least two data blocks.

In a further exemplary embodiment of the computer readable medium above,generating the pre-fetch information is further based on informationprovided by the host, and/or rules in a controller for the memorydevice.

In another exemplary embodiment of any one of the computer readablemedia above, each access command of the one or more access commands isassociated with index information including a context identifier, a tasktag, a pre-fetch identifier and/or a group number.

In a further exemplary embodiment of the computer readable medium above,the one or more access commands include a first access command and asecond access command, and the first access command and the secondaccess command include identical index information.

In another exemplary embodiment of the computer readable medium above,receiving the one or more access commands includes receiving a firstaccess command at a first time including first index information,receiving a second access command at a second time after the first time,where the second access command includes second index information whichdiffers from the first index information, and receiving a third accesscommand at a third time after the second time including the first indexinformation.

In a further exemplary embodiment of the computer readable medium above,generating the pre-fetch information includes linking a last data blockaccessed in response to the first access command to a first data blockaccessed in response to the third access command.

In another exemplary embodiment of the computer readable medium above,generating the pre-fetch information includes starting a new linkingdata session for a first data block accessed in response to the thirdaccess command. Data blocks accessed in response to access commandshaving the same index information are linked during a linking datasession.

In a further exemplary embodiment of the computer readable medium above,data blocks accessed in response to access commands having matchingindex information are linked during a linking data session, and theactions further include starting a new linking data session in responseto an elapse of a predetermined time after a previous access commandshaving the matching index information, an elapse of time after thelinking data session was started, or a change in a control register.

In another exemplary embodiment of any one of the computer readablemedia above, where generating the pre-fetch information includes linkinga first data block of the at least two data blocks to a nextsubsequently accessed data block of the at least two data blocks.

In a further exemplary embodiment of any one of the computer readablemedia above, the one or more access commands include a read commandand/or a write command.

In another exemplary embodiment of any one of the computer readablemedia above, the pre-fetch information include instructions to pre-fetchat least two blocks when a first block is read.

In a further exemplary embodiment of any one of the computer readablemedia above, the actions further include receiving a first read commandinstructing the memory device to provide a first read data block to thehost; providing the first read data block to the host; determining asubsequent read data block based on the pre-fetch information;pre-fetching the subsequent read data block; after pre-fetching thesubsequent read data block, receiving a second read command instructingthe memory device to provide the subsequent read data block to the host;and providing the pre-fetched subsequent read data block to the host.

In another exemplary embodiment of the computer readable medium above,the actions further include receiving a command to cease generatingpre-fetch information for at least a portion of the memory device; andpreventing generating pre-fetch information when accessing data blocksin the portion of the memory device.

In a further exemplary embodiment of the computer readable medium above,the actions further include receiving one or more additional accesscommands instructing the memory device to access one or more of the twoor more data blocks; and removing the pre-fetch information based on anorder of data blocks accessed in response to the one or more accesscommands.

In another exemplary embodiment of any one of the computer readablemedia above, the memory device includes one or more NAND memory storagedevices.

In a further exemplary embodiment of any one of the computer readablemedia above, the computer readable medium is a non-transitory computerreadable medium (e.g., RAM, ROM, CD-ROM, flash memory, etc.).

In another exemplary embodiment in accordance with this invention, anapparatus is provided for enabling cache read optimization for mobilememory devices. The apparatus includes means for receiving (e.g., aprocessor) one or more access commands, at a memory device from a host,the one or more access commands instructing the memory device to accessat least two data blocks; means for accessing (e.g., a processor) the atleast two data blocks; and means for generating (e.g., a processor), bythe memory device, pre-fetch information for the at least two datablocks based at least in part on an order of accessing the at least twodata blocks.

In a further exemplary embodiment of the apparatus above, the generatingmeans is for generating the pre-fetch information based on informationprovided by the host, and/or rules in a controller for the memorydevice.

In another exemplary embodiment of any one of the apparatus above, eachaccess command of the one or more access commands is associated withindex information including a context identifier, a task tag, apre-fetch identifier and/or a group number.

In a further exemplary embodiment of the apparatus above, the one ormore access commands include a first access command and a second accesscommand, and the first access command and the second access commandinclude identical index information.

In another exemplary embodiment of the apparatus above, the receivingmeans includes means for receiving a first access command at a firsttime including first index information, means for receiving a secondaccess command at a second time after the first time, where the secondaccess command includes second index information which differs from thefirst index information, and means for receiving a third access commandat a third time after the second time including the first indexinformation.

In a further exemplary embodiment of the apparatus above, the generatingmeans includes means for linking a last data block accessed in responseto the first access command to a first data block accessed in responseto the third access command.

In another exemplary embodiment of the apparatus above, the generatingmeans includes means for starting a new linking data session for a firstdata block accessed in response to the third access command. Data blocksaccessed in response to access commands having the same indexinformation are linked during a linking data session.

In a further exemplary embodiment of the apparatus above, data blocksaccessed in response to access commands having matching indexinformation are linked during a linking data session, and the apparatusalso includes means for starting a new linking data session in responseto an elapse of a predetermined time after a previous access commandshaving the matching index information, an elapse of time after thelinking data session was started, or a change in a control register.

In another exemplary embodiment of any one of the apparatus above, thegenerating means includes means for linking a first data block of the atleast two data blocks to a next subsequently accessed data block of theat least two data blocks.

In a further exemplary embodiment of any one of the apparatus above, theone or more access commands include a read command and/or a writecommand.

In another exemplary embodiment of any one of the apparatus above, thepre-fetch information include instructions to pre-fetch at least twoblocks when a first block is read.

In a further exemplary embodiment of any one of the apparatus above, theapparatus also includes means for receiving a first read commandinstructing the memory device to provide a first read data block to thehost; means for providing the first read data block to the host; meansfor determining a subsequent read data block based on the pre-fetchinformation; means for pre-fetching the subsequent read data block;means for receiving, after pre-fetching the subsequent read data block,a second read command instructing the memory device to provide thesubsequent read data block to the host; and means for providing thepre-fetched subsequent read data block to the host.

In another exemplary embodiment of the apparatus above, the apparatusalso includes means for receiving a command to cease generatingpre-fetch information for at least a portion of the memory device; andmeans for preventing generating pre-fetch information when accessingdata blocks in the portion of the memory device.

In a further exemplary embodiment of the apparatus above, the apparatusalso includes means for receiving one or more additional access commandinstructing the memory device to access one or more of the two or moredata blocks; and means for removing the pre-fetch information based onan order of data blocks accessed in response to the one or more accesscommands.

It should thus be appreciated that at least some aspects of theexemplary embodiments of the inventions may be practiced in variouscomponents such as integrated circuit chips and modules, and that theexemplary embodiments of this invention may be realized in an apparatusthat is embodied as an integrated circuit. The integrated circuit, orcircuits, may comprise circuitry (as well as possibly firmware) forembodying at least one or more of a data processor or data processors, adigital signal processor or processors, baseband circuitry and radiofrequency circuitry that are configurable so as to operate in accordancewith the exemplary embodiments of this invention.

Various modifications and adaptations to the foregoing exemplaryembodiments of this invention may become apparent to those skilled inthe relevant arts in view of the foregoing description, when read inconjunction with the accompanying drawings. However, any and allmodifications will still fall within the scope of the non-limiting andexemplary embodiments of this invention.

It should be noted that the terms “connected,” “coupled,” or any variantthereof, mean any connection or coupling, either direct or indirect,between two or more elements, and may encompass the presence of one ormore intermediate elements between two elements that are “connected” or“coupled” together. The coupling or connection between the elements canbe physical, logical, or a combination thereof. As employed herein twoelements may be considered to be “connected” or “coupled” together bythe use of one or more wires, cables and/or printed electricalconnections, as well as by the use of electromagnetic energy, such aselectromagnetic energy having wavelengths in the radio frequency region,the microwave region and the optical (both visible and invisible)region, as several non-limiting and non-exhaustive examples.

Further, the various names used for the described parameters (e.g., ID,TAG, etc.) are not intended to be limiting in any respect, as theseparameters may be identified by any suitable names.

Furthermore, some of the features of the various non-limiting andexemplary embodiments of this invention may be used to advantage withoutthe corresponding use of other features. As such, the foregoingdescription should be considered as merely illustrative of theprinciples, teachings and exemplary embodiments of this invention, andnot in limitation thereof.

What is claimed is:
 1. A method comprising: receiving at least oneaccess command, at a memory device from a host, the at least one accesscommand instructing the memory device to access at least two datablocks; accessing the at least two data blocks; and generating, by thememory device, pre-fetch information for the at least two data blocksbased at least in part on an order of accessing the at least two datablocks.
 2. The method of claim 1, where generating the pre-fetchinformation is further based on at least one of: information provided bythe host, and rules in a controller for the memory device.
 3. The methodof claim 1, where each access command of the at least one access commandis associated with index information comprising at least one of: acontext identifier, a task tag, a pre-fetch identifier and a groupnumber.
 4. The method of claim 3, where the at least one access commandcomprises a first access command and a second access command, and thefirst access command and the second access command comprise identicalindex information.
 5. The method of claim 3, where receiving the atleast one access command comprises: receiving a first access command ata first time comprising first index information, receiving a secondaccess command at a second time after the first time, where the secondaccess command comprises second index information which differs from thefirst index information, and receiving a third access command at a thirdtime after the second time comprising the first index information. 6.The method of claim 5, where generating the pre-fetch informationcomprises linking a last data block accessed in response to the firstaccess command to a first data block accessed in response to the thirdaccess command.
 7. The method of claim 5, where generating the pre-fetchinformation comprises starting a new linking data session for a firstdata block accessed in response to the third access command, where datablocks accessed in response to access commands having the same indexinformation are linked during a linking data session.
 8. The method ofclaim 3, where data blocks accessed in response to access commandshaving matching index information are linked during a linking datasession, and further comprising starting a new linking data session inresponse to one of: an elapse of a predetermined time after a previousaccess commands having the matching index information, an elapse of timeafter the linking data session was started, and a change in a controlregister.
 9. The method of claim 1, where generating the pre-fetchinformation comprises linking a first data block of the at least twodata blocks to a next subsequently accessed data block of the at leasttwo data blocks.
 10. The method of claim 1, where the pre-fetchinformation comprise instructions to pre-fetch at least two blocks whena first block is read.
 11. The method of claim 1, further comprising:receiving a first read command instructing the memory device to providea first read data block to the host; providing the first read data blockto the host; determining a subsequent read data block based on thepre-fetch information; pre-fetching the subsequent read data block;after pre-fetching the subsequent read data block, receiving a secondread command instructing the memory device to provide the subsequentread data block to the host; and providing the pre-fetched subsequentread data block to the host.
 12. The method of claim 1, furthercomprising receiving a command to cease generating pre-fetch informationfor at least a portion of the memory device; and preventing generatingpre-fetch information when accessing data blocks in the portion of thememory device.
 13. The method of claim 1, further comprising receivingat least one additional access command instructing the memory device toaccess at least one of the at least two data blocks; and removing thepre-fetch information based on an order of data blocks accessed inresponse to the at least one additional access command.
 14. An apparatuscomprising: at least one processor; and at least one memory deviceincluding computer program code that is executable by the at least oneprocessor to perform acts comprising: receiving at least one accesscommand, at a memory device from a host, the at least one access commandinstructing the at least one memory device to access at least two datablocks; accessing the at least two data blocks; and generating, by theat least one memory device, pre-fetch information for the at least twodata blocks based at least in part on an order of accessing the at leasttwo data blocks.
 15. The apparatus of claim 14, where generating thepre-fetch information is further based on at least one of: informationprovided by the host, and rules in a controller for the memory device.16. The apparatus of claim 14, where each access command of the at leastone access command is associated with index information comprising atleast one of: a context identifier, a task tag, a pre-fetch identifierand a group number.
 17. The apparatus of claim 16, where, when receivingthe at least one access command, the acts further comprise: receiving afirst access command at a first time comprising first index information,receiving a second access command at a second time after the first time,where the second access command comprises second index information whichdiffers from the first index information, and receiving a third accesscommand at a third time after the second time comprising the first indexinformation.
 18. A non-transitory computer readable medium encoded withcomputer program code that is executable by one or more processors toperform acts comprising: receiving at least one access command, at amemory device from a host, the at least one access command instructingthe memory device to access at least two data blocks; accessing the atleast two data blocks; and generating, by the memory device, pre-fetchinformation for the at least two data blocks based at least in part onan order of accessing the at least two data blocks.
 19. Thenon-transitory computer readable medium of claim 18, where each accesscommand of the at least one access command is associated with indexinformation comprising at least one of: a context identifier, a tasktag, a pre-fetch identifier and a group number.
 20. The non-transitorycomputer readable medium of claim 18, where: data blocks accessed inresponse to access commands having matching index information are linkedduring a linking data session, and the acts further comprise: starting anew linking data session in response to one of: an elapse of apredetermined time after a previous access commands having the matchingindex information, an elapse of time after the linking data session wasstarted, and a change in a control register.